Field Programmable Processor Array
Goal
Develop a low-power, radiation-tolerant, high-throughput reconfigurable data processor chip for spacecraft instruments.
Sponsor
NASA Goddard Space Flight Center
FPPA Software and Applications
Prototype Chip
Die area: 7 x 7 mm
Pins: 200 pins of a 208 pin flat pack package
Total gate count: 241,306 gates
Latches: 8,192
Flip flops: 4,850
Combinational logic gates: 229,264
Clock speed: 33 MHz
Single clock domain, no PLLs or clock recovery circuits
Static CMOS logic synthesized from VHDL
Program Memory: 64-bit x 128 program memory “word”
Synthesized into 64 1x128 latch arrays.