Develop reconfigurable data processing capability for high-throughput, low-power spacecraft instrument data processing.
The idea of reconfigurable computing is to build a computer that "rewires" itself on the fly to optimize its architecture for the computing problem at hand, promising maximum throughput with minimum size and energy. Reconfigurable computing's greatest potential may be in data-intensive, streaming applications such as we find in spacecraft instruments: signal processing, image processing and analysis, hyperspectral imaging, space-based radar. A conventional, sequential computer achieves computational agility by executing different instructions one at a time on fixed hardware. In order to maximize throughput, advanced processors invest significant resources in on-board cache memory and complex control structures.
In contrast, a reconfigurable computer minimizes memory and control structures, and instead invests its resources in the data path, the part that actually does the computing. Flexibility comes through reconfigurable function blocks and interconnect, achieving "the performance of dedicated hardware with the flexibility of software".
Our efforts focus on reconfigurable computing for spacecraft instruments. The
The key component is the Field Programmable Processor Array (FPPA), a dedicated processor chip containing 16 processing elements, which can be configured to perform different functions - multiplication, addition, logic, data path formatting, switching - and woven into a synchronous dataflow network.
The FPPA is designed so that multiple FPPA chips can be tiled to form a larger data path network. The Reconfigurable Platform will incorporate multiple FPPA chips along with reconfigurable memory and reconfigurable interconnect to form a board-level computing platform.
A new processor requires a new approach to software. In parallel with the FPPA chip, the Reconfigurable Computing Team, lead by Dr. David Buehler, is developing the software tools necessary to program, simulate and run FPPA chips and the platform.
To build a large array of floating-point computational units would require more silicon area and power consumption than our spacecraft applications can tolerate, so the FPPA implements fixed point arithmetic. Floating point arithmetic is convenient for the programmer, but fixed point can but much more efficient. Designing fixed point data paths that minimize computational error is difficult, however, and there is a shortage of software tools to help the designer. This research is aimed at simplifying the generation of optimal fixed-point computational data paths for the FPPA and for all fixed-point machines.