ECE240 – Digital Logic

Spring 2008

Instructor:           Gregory W. Donohoe, PhD, PE

                                Office: BEL210

                                Tel: 208.885.6707

                                Email: gdonohoe@uidaho.edu

 

Meets:                 MWF, 9:30 – 10:20 AM, BEL205

Office Hours:     Tuesdays & Thursdays 9:00 – 11:00 and by appointment

Class Web page:          http://www.ece.uidaho.edu/ee/digital/donohoe/ECE240/

Lab web page:                   http://www.ece.uidaho.edu/ee/digital/donohoe/ECE241/

Text:                      David M. Harris & Sarah L. Harris, Digital Design and Computer Architecture, Elsevier, 2007.  ISBN 13: 978-0-12-370497-9.

Prerequisites:   A basic understanding of electricity, basic computer literacy.

Syllabus

Course Description

 

ECE 240 Digital Logic (3 cr). Number systems, truth tables, logic gates, flip-flops, combinational and synchronous sequential circuits using Small Scale Integrated Circuits, Medium Scale Integrated Circuits, and programmable devices; intro to digital systems and basic microprocessor architecture. Prereq: Phys 212. Coreq: ECE 241.

 

ECE 241 Logic Circuit Lab (1 cr). Open lab to accompany ECE 240. Design and construction of combinational and synchronous sequential logic circuits. Prereq: Phys 212. Coreq: ECE 240.

 

This is a first course in the concepts of digital system design. Digital systems are everywhere, from laptop computers to cell phones. A modern car has 50 embedded computers that control everything from the engine and the brakes to the stereo. In this course, you will learn what these systems are made of, how they work, and how to design them.  The course covers the mathematical language of computing systems, the fundamental building blocks, and how these are put together to make computing devices. In the lab, you will learn to implement digital systems using the VHDL hardware description language to configure programmable logic devices called Field Programmable Gate Arrays (FPGAs).

Grading

Homework:        10%

Quizzes:               20%

Exams:                  70%

Homework will be assigned weekly (approximately). Homework is due at the beginning of class. In-class quizzes will be given periodically. There will be three in-class exams and a comprehensive final exam.

 

Key Dates

Feb 15: Exam #1

Mar 21: Exam #2

Apr 18: Exam #3

May 5:  Final Exam

Handouts (PDF)

Simple VHDL example 1

Simple VHDL example 2 with internal nodes

VHDL examples 3 & 4

VHDL divide-by-3 state machines

VHDL bit detector state machines

Random Access Memory in VHDL

Homework Assignments (PDF)

Homework #1

Homework #2

Homework #3

Homework #4

Homework #5

Homework #6

Homework #7

 

Homework Solutions (PDF)

Homework #1 solutions

Homework #2 solutions

Homework #3 solutions

Homework #4 solutions

Homework #5 solutions

Homework #6 solutions – corrected

Homework #7 Solutions

 

Quiz Solutions (PDF)

 

Quiz #2 solutions

Exam Solutions (PDF)

 

Exam 1 Solutions