ECE240 Digital Logic
Spring 2009
Instructor: Gregory W. Donohoe, PhD, PE
Office: BEL210
Tel: 208.885.6707
Email: gdonohoe@uidaho.edu
Meets: MWF, 8:30 9:20 AM, EP216
Office Hours: TBD
Class Web page: http://www.ece.uidaho.edu/ee/digital/donohoe/ECE240/
Lab web page: http://www.ece.uidaho.edu/ee/digital/donohoe/ECE241/
Text: David M. Harris & Sarah L. Harris, Digital Design and Computer Architecture, Elsevier, 2007. ISBN 13: 978-0-12-370497-9.
Prerequisites: A basic understanding of electricity, basic computer literacy.
ECE 240 Digital Logic (3 cr). Number systems, truth tables, logic gates, flip-flops, combinational and synchronous sequential circuits using Small Scale Integrated Circuits, Medium Scale Integrated Circuits, and programmable devices; intro to digital systems and basic microprocessor architecture. Prereq: Phys 212. Coreq: ECE 241.
ECE 241 Logic Circuit Lab (1 cr). Open lab to accompany ECE 240. Design and construction of combinational and synchronous sequential logic circuits. Prereq: Phys 212. Coreq: ECE 240.
This is a first course in the concepts of digital system design. Digital systems are everywhere, from laptop computers to cell phones. A modern car has 50 embedded computers that control everything from the engine and the brakes to the stereo. In this course, you will learn what these systems are made of, how they work, and how to design them. The course covers the mathematical language of computing systems, the fundamental building blocks, and how these are put together to make computing devices. In the lab, you will learn to implement digital systems using the VHDL hardware description language to configure programmable logic devices called Field Programmable Gate Arrays (FPGAs). At the end of this class, you will be able to design simple digital systems. It will also prepare you for further study of digital systems and computing technology.
Grading
Homework: 10%
Quizzes: 20%
Exams: 70%
Homework will be assigned weekly (approximately). Homework is due at the beginning of class. In-class quizzes will be given periodically. There will be three in-class exams and a comprehensive final exam.
Key Dates
Wednesday, Feb 18 Exam #1
Friday, March 27 Exam #2
Friday, May 1 Exam #3
Monday, May 18 Final Exam
Lecture 17: Simple VHDL Examples
Lecture 37: VHDL State Machines
Homework #4 Solutions - Corrected
ECE240 Schedule Spring 2009
|
Nr |
Day |
Date |
Topics |
Comments |
|
1 |
Wed |
Jan 14 |
Introduction |
|
|
2 |
Fri |
Jan 16 |
Lab introduction & demo |
|
|
3 |
Mon |
Jan 19 |
MLK Day No class |
|
|
4 |
Wed |
Jan 21 |
Intro to number systems |
HW #1 assigned |
|
5 |
Fri |
Jan 23 |
Binary arithmetic |
Text 1.4 |
|
6 |
Mon |
Jan 26 |
Signed arithmetic |
Text 1.4 |
|
7 |
Wed |
Jan 28 |
Logic gates |
Text 1.5; HW#2 |
|
8 |
Fri |
Jan 30 |
Logic gates, Lab 2 preview |
Text 2.1 |
|
9 |
Mon |
Feb 2 |
Logic gates |
Text 2.1 |
|
10 |
Wed |
Feb 4 |
Into to Boolean Algebra |
Text 2.3 |
|
11 |
Fri |
Feb 6 |
Boolean Algebra |
Text 2.4 |
|
12 |
Mon |
Feb 9 |
Logic Minimization |
Text 2.5; HW#3 |
|
13 |
Wed |
Feb 11 |
Multilevel Logic |
Text 2.6 |
|
14 |
Fri |
Feb 13 |
Combinational building blocks |
|
|
-- |
Mon |
Feb 16 |
Presidents Day No class |
|
|
15 |
Wed |
Feb 18 |
Exam 1 preview; comb. building blks |
Text 2.8 |
|
16 |
Fri |
Feb 20 |
Exam #1 |
|
|
17 |
Mon |
Feb 23 |
Intro to VHDL |
Text 4.1, 4.2.1-4.2.2 |
|
18 |
Wed |
Feb 25 |
More VHDL |
Text 4.2 (all) |
|
19 |
Fri |
Feb 27 |
Intro: Karnaugh maps |
Text 2.7 |
|
20 |
Mon |
Mar 2 |
Karnaugh maps; gate delays |
Text 2.7, 2.9. HW #4 |
|
21 |
Wed |
Mar 4 |
Iterative Logic |
|
|
22 |
Fri |
Mar 6 |
Latches & Flip Flops |
Text 3.1-3.3; skip 3.2.7 |
|
23 |
Mon |
Mar 9 |
Latches & Flip Flops |
Text 3.1-3.3; skip 3.2.7 |
|
24 |
Wed |
Mar 11 |
Sequential Logic |
Text 3.3 |
|
25 |
Fri |
Mar 13 |
Finite State Machines; |
Text 3.4 |
|
-- |
Mon |
Mar 16 |
Spring Break! |
Mid-term grades due |
|
-- |
Wed |
Mar 18 |
|
|
|
-- |
Fri |
Mar 20 |
|
|
|
26 |
Mon |
Mar 23 |
Arith-Logic Unit (ALU); FSMs; HW #5 |
Text 3.4, and 5.2.4 |
|
27 |
Wed |
Mar 25 |
FSMs |
Text 3.4 |
|
28 |
Fri |
Mar 27 |
Sequential Logic in VHDL |
HW#5 due |
|
29 |
Mon |
Mar 30 |
More FSMs |
|
|
30 |
Wed |
Apr 1 |
Review for Exam 2 |
HW #5 returned |
|
31 |
Fri |
Apr 3 |
Exam #2 emphasis HW#4 & 5 |
|
|
32 |
Mon |
Apr 6 |
More sequential logic/VHDL |
Text 4.4 |
|
33 |
Wed |
Apr 8 |
Moore + Mealy, One-hot encodings |
Text 3.4.3 |
|
34 |
Fri |
Apr 10 |
Sequential Circuit Timing |
Text 3.5 |
|
35 |
Mon |
Apr 13 |
Sequential Circuit Timing |
HW #6 |
|
36 |
Wed |
Apr 15 |
Misc. Seq. Ckt. Topics |
|
|
37 |
Fri |
Apr 17 |
State Machines in VHDL |
|
|
38 |
Mon |
Apr 20 |
Metastabilty |
Text 3.5.4; HW #6 due |
|
39 |
Wed |
Apr 22 |
Mestasbiliity; Parallelism |
Text 3.6; HW #7 |
|
40 |
Fri |
Apr 24 |
Parallelism |
|
|
41 |
Mon |
Apr 27 |
Comb. Logic modules |
Text Ch 5; HW #7 due |
|
42 |
Wed |
Apr 29 |
|
HW #7 returned; Exam 3 preview |
|
43 |
Fri |
May 1 |
Exam 3 |
|
|
44 |
Mon |
May 4 |
Work on Lab 14: Pico_Processor |
No-exam week |
|
45 |
Wed |
May 6 |
Work on Lab 14 |
No-exam week |
|
|
Fri |
May 8 |
Final exam preview; Lab 14 |
No-exam week |
|
|
Fri |
May 15 |
Final Exam 7:30 9:30 AM |
Corrected Date |