ECE 241 Digital Logic Lab (Fall 2007)

Lab TA: Damian Sanchez, damians@vandals.uidaho.edu

Lab Hours: Open lab

Grades on lab experiments are separate from ECE 240 and determine the grade for ECE 241. There will be approximately twelve labs throughout the semester and all are mandatory. (Experiments that are not fully functional may be submitted for partial credit, if on time, but a report only earns little credit.) Late assignments are not accepted. Labs will be conducted in GJL 210. Each student should bring the following to each lab. Students must work alone.

· Lab notebook (for recording information, observations, and data)

· Pre-lab assignment (if applicable), ready to turn in

· Lab handout for scheduled experiment

Lab Schedule

· Each lab lasts one week, starting on Monday.

· Each lab is to be demonstrated to the instructor or TA by 5:00 PM on the Friday of the lab week.

· The lab report is due the following Monday.

· Prelab assignments are due at the start of the lab. Be sure to read the lab assignments and start you prelab work well ahead of time.

Lab	Start Date	Topics	Comments
	Jan 9	Classes start
1	Jan 14	Know your environment
2	Jan 21	Comb. logic design
3	Jan 28	Real circuits	Cancelled
4	Feb 4	Blinky & VHDL
5	Feb 11	7-segment decoder redux
6	Feb 25	Structural VHDL – ripple carry adder
7	Mar 3	Continue ripple_carry adder
	Mar 10	SPRING BREAK!	Midterm grades due
8	Mar 17	Pico ALU
	Mar 24	Continue Pico ALU
9	Mar 31	Keep On Counting!
11	Apr 7	Light them Lights
12	Apr 14	Light them Lights in VHDL
13	Apr 21	Pico-processor
14	Apr 28
	May 5	FINAL EXAM WEEK	Lab 14 report due

Lab Experiments

1. Getting to Know your Environment.

2. Combinational Logic Design. Pre-lab: Hand-drawn schematic of circuit.

3. Real Circuits. Pre-lab (section 8): Lab 3 cancelled!

4. Implementing Combinational Logic Circuits. Pre-lab collected at the start of lab.

5. Blinky and VHDL! Pre-lab: Read sections 4.0 - 4.2.2 of the text (only VHDL!). Report.

6. Seven Segment Decoder, Redux. Pre-lab: draft of your code (typed or handwritten). Read these examples for tips on how to implement this lab. Report.

7. Structural VHDL and Iterative Circuits. Two week lab. Read this example for implementing structural VHDL.

Week 1: complete your full adder implementation with behavioral simulation. Start on full adder (Nothing to turn in at this point.)

Week 2: finish and demo the full adder, complete report.

8. Pico ALU. 4-bit ALU to be used in the Pico Processor we will design later. As a guide to coding this, refer to the updated 4-bit adder-subtractor example here.

9. Keep Counting. 4-bit counter implemented in VHDL, to be downloaded and run on the Digilent board.

10. Light them Lights! A state machine to cycle through a pattern of lights. Design by hand and enter as a schematic. Pre-lab to be approved by the TA before you start the lab.

11. Light them Lights in VHDL. Repeat the previous lab, but implement your design as a VHDL module. No prelab to turn in.

12. Pico Processor. Design and demonstrate a simple programmable computer, using slide switches to input data and instruction. Prelab: state graph (bubble diagram) of your Finite State Machine. Here’s a PDF file of the Pico Processor Data Path.

Basic Process

· Design your circuit with paper and pencil

· Create new project and enter your design sources (schematics or VHDL)

· Create a test bench waveform and perform behavioral (i.e., pre-synthesis) simulation

· Assign package pins

· Perform synthesis and implementation

· Perform post-route simulation

· Download design and demo

· Print design summary and obtain signature

· Turn in design sources, simulation results, signed design summary, and report

Download Checklist

Do not download your design to the FPGA (i.e., program the part) until you have completed the following checklist. Failure to do so may damage the component and result in a fine.

· Check for any warnings or errors. Some warnings may be ok, but you can not ignore errors. If unsure, check with the instructor

· Verify the part number and package type

· Verify the pin assignment by looking at the pad report

· Verify that the JTAG clock is selected as the “startup clock”

· Verify that the programming cable and power cable are connected

· Verify that the programming switch is in the JTAG position

· No blanks or non-alphanumeric characters in path or file name

· The entity name of a VHDL module must match the file name with a vhd extension