Design a finite state machine for driving three LEDs. It has two inputs, reset and x, and three outputs, which will drive three LEDs. Here’s the behavior.
If reset = 1, the FSM waits in an idle state with all LEDs off.
When reset=0:
If x = 1, the FSM cycles through lighting each LED, one at a time, in a rotating pattern left-to-right.
If x=0, the FSM lights the outer two LEDs leaving the middle one off, then lights the middle LED and turns off the outer two, alternating each clock cycle.
If x changes while reset = 0, this has no effect; the state machine will just keep repeating the same pattern until reset =1, when it goes back into the idle state. Only then will x have an effect.
Design the system, and turn in a bubble diagram, state transition diagram, state transition and output equations, and a sketch of your design.
You will enter your design as a schematic. To see the lights blinking, you will need to slow the clock down with a Linear Feedback Shift Register (LFSR). The LFSR is written in VHDL. You will need to convert it to a symbol in order to put it into your schematic.
Implement your FSM using schematic entry, with flip-flops or registers, muxes, decoders, and/or primitive logic gates as needed. (No VHDL!) Next, perform a behavioral simulation to verify operation. Finally, download the following VHDL file, representing an LFSR (or cut and paste from below), create a symbol, and instantiate it in your schematic in order divide down the board oscillator. Don't forget to include the IBUFG symbol for the clock!
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-- Linear Feedback Shift Register to divide the clock down
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lfsr is
port (fclk: in std_logic;
clk: out std_logic);
end lfsr;
architecture Behavioral of lfsr is
signal sclk: std_logic;
begin
process (fclk)
variable sreg : std_logic_vector(1 to 21);
begin
if rising_edge(fclk) then
if (conv_integer(sreg) = 0) then
sclk <= not sclk;
end if; -- equals zero
sreg := (sreg(19) xnor sreg(21)) & sreg(1 to 20);
end if; -- rising_edge
end process;
clk <= sclk;
end Behavioral;