ECE 241 Lab 12: Pico Processor

Objective

Use VHDL to design a controller for the Pico Processor.  Understand the sequence of operations for a programmable processor.

This is a two-week lab.

Pre-lab

Turn in at the start of the lab a complete state graph of your FSM.

Experiment

Develop the architecture for the Pico Processor controller and verify your design through simulation. Combine your ALU and controller using pico.vhd and verify on the experiment board using pico.ucf. Demonstrate the working design to the instructors.

Your controller must support the following instruction set.

Instruction	Opcode	Operation
ADD	0000	rega <= rega + regb; update CCR
SUB	0001	rega <= rega - regb; update CCR
AND	0010	rega <= rega AND regb; update CCR
OR	0011	rega <= rega OR regb; update CCR
CMPL	0100	rega <= not(rega); update CCR
IN A	0101	rega <= SW(1-4); update CCR
OUT A	0110	out <= rega; CCR unchanged
MOV	0111	regb <= rega; CCR unchanged
STOP	1111	Stop and return to reset state

The inputs and outputs of the controller are shown in the template below.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pico_cntrl is

    Port ( clk : in std_logic; rst : in std_logic; go : in std_logic;

           ir : in std_logic_vector(3 downto 0);

           ld_in : out std_logic; ld_out : out std_logic;

           sel : out std_logic; ld_ir : out std_logic;

           ld_a : out std_logic; ld_b : out std_logic;

           ld_ccr : out std_logic; ld_tmp : out std_logic);

end pico_cntrl;

architecture Behavioral of pico_cntrl is

begin

end Behavioral;