ECE 241 Lab 2 – Combinational Logic Design

Objective

Design, verify, and implement a 2-bit binary comparator. Your design will accept two, 2-bit unsigned numbers A and B and activate one output GE: Greater-than-or-equal-to.

Pre-Lab (5 pts)

Bring to lab a preliminary design of your comparator. It must include a truth table for the output and a gate-level schematic.

Experiment (10 pts)

1. Verify your design using behavioral simulation of your design
2. Assign package pins
3. Perform post-route simulation and observe the simulated circuit delays, compared to behavioral simulation
4. Download your design to the Digilent board and verify using switches and LED
5. Demonstrate all of the above to the TA

Report (5 pts)

Turn in a brief, professional report that describes your design process and results. Elaborate on any problems you encountered. Finally, attach to your report hardcopies of your schematic, behavioral and post-route simulations, and the signed design summary.

Specifics

Connect SW1-SW4 on the DIO1 board as inputs and LD1 as outputs. See the Pin Table linked on the lab web page for the proper FPGA pins.

Do not use IBUFG symbols on the switch inputs.