ECE 241 Lab 6: 7 Segment Decoder, Redux

Objective

Investigate the use of VHDL for implementing combinational logic functions.

Experiment (15 pts)

1. Use VHDL concurrent statements to implement your binary to seven-segment decoder (no processes!)

· You may use concurrent signal assignments with logical operators, conditional signal assignments, or selected signal assignments.

· See VHDL examples 4.3, 4.5, and 4.6 from Harris & Harris.

2. Perform post-synthesis simulation of your design (all 16 combos).
3. Download your design to the Digilent board and verify using switches and the 7-segment display.

Report (5 pts)

Turn in a brief, professional report that describes your design process and results. Comment on the “efficiency” of VHDL compared to schematics. Elaborate on any problems you encountered. Finally, attach to your report hardcopies of your VHDL, post-synthesis simulation, and the signed project summary.