Use VHDL to model a binary counter and display the count.
Use a VHDL process that models a four-bit binary up counter with a count enable and connect the outputs of the counter to a seven segment display, using your decoder from an earlier lab.
The clock source for your sequential circuit will come from the oscillator on the D2XL board FPGA pin 91). This oscillator is very fast and we would not be able to verify your counter visually. Consequently, we will first divide down the clock using a linear feedback shift register (LFSR). Next, we will create a count enable pulse, one clock cycle wide, using a “pulse generator” circuit. This circuit will generate a single pulse, one clock period wide, in response to a falling edge from one of the pushbuttons on the DIO1 board.
In this skeleton template (or cut and past the template from below.) fclk is the oscillator clock and sclk is the divided down clock. Similarly, cnt_enb_btn is the button signal and cnt_enb_deb is the generated pulse.
Unfortunately, these circuits require many, many, (way too many!) simulation cycles. Thus, I have included in the code, signal assignments that allow you to “easily” switch between using the fclk signal and the sclk signal, simply by uncommenting the desired signal. In this way, you can write your counter model using clk and cnt_enb.
You will need to name your signals and assign pins appropriately. The synthesis tool should automatically insert the IBUFG symbol automatically (as done in Lab 1). Simulate your design after synthesis, post-P&R, before downloading to the board. Don't forget to connect the anode signal for the seven-segment display and change the sources for clk and cnt_enb before downloading to the board.
Turn in a brief, professional report that describes your design process and results. Comment on any observations during simulation or hardware testing. Elaborate on any problems you encountered. Finally, attach to your report hardcopies of your VHDL, post-synthesis simulation, and the project summary.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( fclk : in std_logic; -- fclk is the fast board clock
-- add more signals as
needed!!!
cnt_enb_btn : in std_logic);
end counter;
architecture Behavioral of counter is
signal clk,
sclk, cnt_enb, cnt_enb_deb : std_logic;
begin
--
-- insert your counter model
here, using clk and cnt_enb
--
--
--
--
--
--
--
-- Pick one and comment out
the other
clk
<= fclk; -- used for simulation
-- clk
<= sclk; -- used for demo on board
-- Pick one and comment out
the other
cnt_enb <= cnt_enb_btn; -- used for simulation
-- cnt_enb <= cnt_enb_deb; -- used for demo on board
-- Debounce
the button and generate a pulse
process (clk)
variable sreg1 : std_logic_vector(3
downto 0);
begin
if rising_edge(clk) then
if (sreg1 =
"1110") then cnt_enb_deb <= '1';
else cnt_enb_deb <= '0';
end if;
sreg1 := cnt_enb_btn & sreg1(3 downto
1);
end if;
end process;
-- divide down fclk using an LFSR
process (fclk)
variable sreg
: std_logic_vector(1 to 21);
begin
if rising_edge(fclk) then
if
(conv_integer(sreg) = 0)
then
sclk
<= not sclk;
end
if; -- equals zero
sreg := (sreg(19) xnor sreg(21)) & sreg(1 to 20);
end if; -- rising_edge
end process;
end Behavioral;