LECE241 – Digital Circuits Lab

Spring 2009

Instructor:           Gregory W. Donohoe, PhD, PE

                                Office: BEL210

                                Tel: 208.885.6707

                                Email: gdonohoe@uidaho.edu

Lab TA:                 Damian Sanchez Moreno, damians@vandals.uidaho.edu

Lab Hours:          Open lab

Grades on lab experiments are separate from ECE 240 and determine the grade for ECE 241. There will be approximately twelve labs throughout the semester and all are mandatory. (Experiments that are not fully functional may be submitted for partial credit, if on time, but a report only earns little credit.) Late assignments are not accepted. Labs will be conducted in GJL 210. Each student should bring the following to each lab. Students must work alone.

· Lab notebook (for recording information, observations, and data)

· Pre-lab assignment (if applicable), ready to turn in

· Lab handout for scheduled experiment

Lab Schedule

· Each lab lasts one week, starting on Monday.

· Each lab is to be demonstrated to the instructor or TA by 5:00 PM on the Friday of the lab week.

· The lab report is due the following Monday.

· Prelab assignments are due at the start of the lab. Be sure to read the lab assignments and start you prelab work well ahead of time.

Labs

Lab 1: Getting to Know Your Environment (Lab1_know_env.pdf)

Helpful Handout for Lab 1 (Lab 1_Handout1.pdf)

Lab 2: Combinational Logic Design (Lab_2_comb_logic.pdf)

Lab 3: Real Circuits. Also download and print the Lab 3 Handout. (Lab_3_real_circuits.pdf)

Also download the Lab 3 Handout (Lab_3_prelim.pdf)

Lab 4: Implementing Combinational Logic Circuits (Lab_4_Combinational_Logic.pdf)

Lab 5: Blinky and VHDL (Lab_5_Blinky+VHDL.pdf)

Lab6: Seven-segment Decoder Redux (Lab_6_seven_seg_redux.pdf)

Lab 7: Structural VHDL and Iterative Circuits

Instructions on post P&R testbench (testbench.pdf)

Simulation script file sample.do

Lab 8: Wimpy ALU with Multiplexers (Lab_8_Wimpy_ALU.pdf)

Lab 9: Latch or Flip-Flop? (Lab_9_Latch_or_FF.pdf)

Lab 10: Keep on Counting – 4 bit counter  (Lab_10_Keep_on_Counting.pdf)

Use this skeleton template as explained in the lab (skeleton_template.txt)

Lab 11: Moore or Mealy Machine? (Lab_11_Moore_or_Mealy.pdf)

      Follow this handout to display your system state in the waveform plot (Lab11s09_Handout.pdf)

Lab 12: Light them Lights in VHDL (Lab_12_light_lights_VHDL)

      Skeleton template for Lab 12 (lights_template.vhd)

      LFSR to slow clock (lfsr.vhd)

Lab 13: Pico-ALU (Lab_13_Pico_ALU.pdf)

      VHDL template for Lab 13 (Pico_ALU.vhd)

Lab 14: Pico-Processor (Lab_14_Pico_Processor.pdf)

      VHDL template for Lab 14 (pico.vhd)

UCF file for Lab 14 (pico.ucf)

Tips for Lab 14 (Lab_14_Tips.pdf)

Basic Process

· Design your circuit with paper and pencil

· Create new project and enter your design sources (schematics or VHDL)

· Create a test bench waveform and perform behavioral (i.e., pre-synthesis) simulation

· Assign package pins

· Perform synthesis and implementation

· Perform post-route simulation

· Download design and demo

· Print design summary and obtain signature

· Turn in design sources, simulation results, signed design summary, and report

Download Checklist

Do not download your design to the FPGA (i.e., program the part) until you have completed the following checklist. Failure to do so may damage the component and result in a fine.

· Check for any warnings or errors. Some warnings may be ok, but you can not ignore errors. If unsure, check with the instructor

· Verify the part number and package type

· Verify the pin assignment by looking at the pad report

· Verify that the JTAG clock is selected as the “startup clock”

· Verify that the programming cable and power cable are connected

· Verify that the programming switch is in the JTAG position

· No blanks or non-alphanumeric characters in path or file name

· The entity name of a VHDL module must match the file name with a vhd extension

Reference Material

Sample Lab Reports

Digilent Board Documentation: D2XL FPGA Board

Digilent Board Documentation: DIO1 I/O Board

D2XL->DIO1 Pin Table

Sample UCF file (sample_file.ucf) and Do file (sample_do.do) for Post P&R Simulation

Xilinx naming conventions and recommendations

Xilinx ISE Documentation:

· Xilinx ISE Quick Start Tutcorial

· Xilinx ISE Manuals

· Xilinx Library Guide (or see “Functional Categories” under “Libraries Guide” in ISE manual)