-- Memory, four bit wide, 64 bits deep. This memory does not have
-- a registered output; the output always contains the contents 
-- the 'address' points to
--
-- Greg Donohoe     20 Apr 05
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

package mem_defs is
   constant MEM_SIZE: integer := 64;
   constant WORD_SIZE: integer := 4;
   constant ADDR_SIZE: integer := 6; 
end mem_defs;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mem_defs.all;

entity memory is
   port ( we: in std_logic;
           d: in std_logic_vector(WORD_SIZE-1 downto 0);
     address: in std_logic_vector(ADDR_SIZE-1 downto 0);
           q: out std_logic_vector(WORD_SIZE-1 downto 0)
        );
end memory;

architecture execute of memory is
 --  type word is array (WORD_SIZE-1 downto 0) of std_logic;
   type mem_array is array (MEM_SIZE-1 downto 0) of std_logic_vector(WORD_SIZE-1 downto 0);
   signal mem: mem_array;
 begin
    process (address, mem, we, d)
       variable iaddress: integer range 0 to 63;
    begin
       iaddress := conv_integer(address);
       if (we = '1') then
          mem(iaddress) <= d;
       end if;
	  q <= mem(conv_integer(address));
    end process;
 end execute;