library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity add4 is
port (A,B: in std_logic_vector(3 downto 0);
      S: out std_logic_vector(3 downto 0)
      );
end add4;
      
architecture arch of add4 is
begin
   process (A, B)
   begin
      S <= A + B;
   end process;
end arch;