ECE440: Digital Systems Engineering

Spring 2005

Instructor              Gregory W. Donohoe, PhD, PE

                                    Office: BEl210

                                    Tel: 885-6707

                                    Email: donohoe@ece.uicaho.edu

Office Hours         MWF 1:00 – 2:00

Class Time            MWF 2:30 – 3:20 PM

Location                 JEB026

Web Page www.ece.uidaho.edu/ee/digital/ECE440

Text                          Douglas L. Perry, VHDL: Programming by Example, 4^th Ed, McGraw-Hill, 2002. ISBN 0071400702.

Syllabus ECE 440 Syllabus (PDF)

Teaching Sriharsha Mallajosyula

Assistant mall2694@uidaho.edu

Handouts

Lecture #1: Microelectronic System Economics

Lecture #3: NAND Gate VHDL Examples

Compact MUX Example

Lecture #6: Structural multiplexer (PDF or Word)

Lecture #8: Gray code counter

Source code (PDF)

Source code (VHDL)

Stimulus file (TXT)

Waveform plot (PDF)

Lecture #10: Multiplexer and testbench (PDF or Word)

Lecture #11: Gray code counter with package (PDF or Word)

Lecture #13: Xilinx Spartan II architecture excerpt (PDF)

Complete Spartan II family document (PDF)

Lecture #14: Bit pattern detector (PDF) or (Word)

Waveform plot (PDF)

Lecture #15: Simple counter to synthesize (PDF) or (Word)

Lecture #17: Averager specification (PDF) or (Word)

Averager VHDL source, beta version (PDF) or (Word)

Waveform plot (PDF)

Lecture #21: D2SB Demo (PDF), (Word), (.vhd), (.ucf), bit file

Lecture #24: D2SB_DIO5 Demo: bit file

Lecture #27: Spartan Select I/O Interface (PDF)

Lecture #28: Signal Integrity References

o High-Speed Digital Design: A Handbook of Black Magic, Howard Johnson and Martin Graham, Prentice Hall PTR, 1993.

o Digital Techniques for High-Speed Design, Tom Granberg, Prentice Hall PTR, 2004.

o Noise Reduction Techniques in Electronic Systems, Henry W. Ott, John Wiley & Sons, 1988.

Lecture #30:

o National Semiconductor, “Voltage Regulator Fundamentals” (PDF)

o Micron, “Bypass Capacitor Selection for High-Speed Designs” (PDF)

Lecture #34: Clock Distribution. Delay Locked Loops in Spartan FPGAs (PDF)

Lecture #36: Memory

VHDL memory module (VHDL)

Testbench waveform for memory module (PDF)

Miscellaneous: Averager: 2^nd version (PDF) or (Word)

Homework

Assignment #1: VHDL Multiplexer

Assignment #2: Four-bit adders

Part 3: adder source code add4.vhd

Assignment #3: Adder testbench

Assignment #4: Burglar alarm arming circuit

Assignment #5: Digilent demo exercises

Class Project

Class Project Specification (PDF)

Project Report Supplement (PDF)

Resources

Reference Designs for Digilent Boards

Hex counter, displays on 7-segment display (.vhd, .ucf) LED colors: lights up color banks of LEDs with pushbutton (.vhd, .ucf)

DIO5 demo: reads buttons and switches, displays on LEDS and 7-segment displays (.vhd, .ucf)

FPGA Development Kits

In this class we will use development boards from Digilent, Inc., in Pullman, WA (www.digilentinc.com). The products we will use are:

D2SB System Board

D2SB Reference Manual

D2SB Schematic

DIO5 I/O Board

DIO5 Reference Manual

DIO5 Schematic

Xilinx ISE Tutorial

Instructional Videos from Digilent (Link)

1. Basic Schematic Capture and Simulation

2. Circuit Simulation (covers ModelSim)

3. Introduction to VHDL

4. Programming the Digilab Board

Electronic Packaging

Here’s a helpful link to a description of electronic package types and names (Surface mount part jargon).

VHDL

The VHDL Cookbook (PDF)

VHDL Math Tricks (PDF)

Xilinx CPLD VHDL Guide (PDF)

Xilinx

Xilinx Resource Center Home Page

Xilinx Logic Handbook (PDF)

Xilinx Constraints Guide (PDF)

Spartan SelectIO Interface (PDF)

Standard Cell Library Data sheets

Tanner 0.5u Standard Cell Library (PDF)

ModelSim

Using ModelSim