------------------------------------------------------------------------ -- dio5_demo.vhd -- Digilab D2SB test configuration for use with DIO5 -- in connector position C. ------------------------------------------------------------------------ -- Author: Chris Canine -- University of Idaho -- ECE 440 - Spring 2005 ------------------------------------------------------------------------ -- -- Inputs: -- sysCLK : in std_logic; -- Main system clock, runs at 50Mhz -- ob_btn : in std_logic; -- Direct input from D2SB onboard button -- dataBuf: inout std_logic_vector(7 downto 0); -- CPLD I/O buffer -- encBtn : in std_logic_vector(3 downto 0)) -- Direct input from encoded buttons -- -- Outputs: -- ob_led : out std_logic; -- Direct output to D2SB onboard LED -- address: out std_logic_vector(5 downto 0); -- DIO5 address being read/written -- lclk : out std_logic; -- Triggers refreshes in the Seven Segment Display -- writeEN: out std_logic; -- DIO5 Write Enable Signal -- chipSEL: out std_logic; -- DIO5 Chip Select Signal -- outEN : out std_logic; -- DIO5 Output Enable Signal -- -- This module is based on the module D2SB-dio5_c.vhd provided as a demo -- by Digilent, Inc. All LCD, VGA and keyboard functions have been removed. -- Otherwise, this module functions the same as the Digilent demo. -- -- This module tests the board combination (C connector) by reading -- the status of the buttons and switches, and mapping the button and -- switch output to the LEDs and SSEG displays on the DIO5. The design -- centers on a state machine that reads and writes the DIO5 registers -- in a recurring sequence. -- -- In operation, the 16 pushbuttons are mapped to the 16 discrete LEDs, and the -- 8 slide switches drive two Sseg displays. Additionally, all buttons are -- directly available on discrete signals into the FPGA. Buttons 0 - 9 are -- avaialble as a 4-bit BCD code; these signals drive digit 3 of the Sseg -- display. Buttons A-F are or'ed together and drive the on-board LED. -- A counter drives the 4th Sseg digit. -- -- Since insufficient room exists in the CPLD to implement full read-write -- capabilities on all registers, the input devices are read-only, and the -- output devices are write-only. Because of this, the input and output -- devices share memory locations. The memory map is: -- -- address read write -- 000 BtnLo LedLo -- 001 BtnHi LedHi -- 010 Swt SsegLo -- 010 - SsegHi -- 100 - LCD instruction -- 101 - LCD DRAM -- 110 LCD - -- ------------------------------------------------------------------------ -- Revision History: -- 03/25/2005 : Created ------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dio5_demo is Port (sysCLK : in std_logic; -- Main system clock, runs at 50Mhz ob_btn : in std_logic; -- Direct input from D2SB onboard button ob_led : out std_logic; -- Direct output to D2SB onboard LED address : out std_logic_vector(5 downto 0); -- DIO5 address being read/written lclk : out std_logic; -- Triggers the digit change in the Seven Segment Display writeEN : out std_logic; -- DIO5 Write Enable Signal chipSEL : out std_logic; -- DIO5 Chip Select Signal outEN : out std_logic; -- DIO5 Output Enable Signal dataBuf : inout std_logic_vector(7 downto 0); -- CPLD I/O buffer encBtn : in std_logic_vector(3 downto 0)); -- Binary Encoded Decimal values of push buttons end dio5_demo; architecture Behavioral of dio5_demo is type state_type is (INIT, RdBtnLo_A, RdBtnLo_B, RdBtnLo_C, RdBtnHi_A, RdBtnHi_B, RdBtnHi_C, RdSwt_A, RdSwt_B, RdSwt_C, WrLEDLo_A, WrLEDLo_B, WrLEDLo_C, WrLEDHi_A, WrLEDHi_B, WrLEDHi_C,WrSsegLo_A, WrSsegLo_B, WrSsegLo_C, WrSsegHi_A, WrSsegHi_B, WrSsegHi_C); signal STATE: state_type; signal cntClk : std_logic_vector(27 downto 0) := "0000000000000000000000000000"; signal BtnLoReg : std_logic_vector(7 downto 0); signal BtnHiReg : std_logic_vector(7 downto 0); signal SwtReg : std_logic_vector(7 downto 0); signal reset : std_logic; --reset signal Ssegcnt : std_logic_vector(3 downto 0); --value displayed on LCD, top 4 MSBs of cntClk begin process (STATE, sysCLK, reset) begin -- Reinitialize system on reset if reset ='1' then STATE <= INIT; elsif rising_edge(sysCLK) then case STATE is when INIT => STATE <= RdBtnLo_A; when RdBtnLo_A => STATE <= RdBtnLo_B; when RdBtnLo_B => STATE <= RdBtnLo_C; when RdBtnLo_C => STATE <= RdBtnHi_A; when RdBtnHi_A => STATE <= RdBtnHi_B; when RdBtnHi_B => STATE <= RdBtnHi_C; when RdBtnHi_C => STATE <= RdSwt_A; when RdSwt_A => STATE <= RdSwt_B; when RdSwt_B => STATE <= RdSwt_C; when RdSwt_C => STATE <= WrLedLo_A; when WrLedLo_A => STATE <= WrLedLo_B; when WrLedLo_B => STATE <= WrLedLo_C; when WrLedLo_C => STATE <= WrLedHi_A; when WrLedHi_A => STATE <= WrLedHi_B; when WrLedHi_B => STATE <= WrLedHi_C; when WrLedHi_C => STATE <= WrSsegLo_A; when WrSsegLo_A => STATE <= WrSsegLo_B; when WrSsegLo_B => STATE <= WrSsegLo_C; when WrSsegLo_C => STATE <= WrSsegHi_A; when WrSsegHi_A => STATE <= WrSsegHi_B; when WrSsegHi_B => STATE <= WrSsegHi_C; when WrSsegHi_C => STATE <= RdBtnLo_A; when others => STATE <= INIT; end case; end if; end process; process (sysCLK, STATE) begin if rising_edge(sysCLK) then -- Divide the clock to provide various smaller clocks cntClk <= cntClk + 1; -- Read values from data registers when appropriate if (STATE = RdBtnLo_B) then BtnLoReg <= dataBuf; elsif (STATE = RdBtnHi_B) then BtnHiReg <= dataBuf; elsif (STATE = RdSwt_B) then SwtReg <= dataBuf; end if; end if; end process; -- Tie input button to reset reset <= ob_btn; Ssegcnt <= cntClk(27 downto 24); -- Counter displayed on DIO5 Sseg display ob_led <= cntClk(23) or reset; -- Blinking onboard LED, solid on reset lclk <= cntClk(16); -- Runs at 763 Hz -- Bus mux and tristate control to setup data bus for writes to DIO5 dataBuf <= BtnLoReg when STATE = WrLedLo_B else -- write LedLoReg in CPLD BtnHiReg when STATE = WrLedHi_B else -- write LedHiReg in CPLD SwtReg when STATE = WrSsegLo_B else -- write SsegLoReg in CPLD Ssegcnt & encBtn when STATE = WrSsegHi_B else -- write SsegHiReg in CPLD "ZZZZZZZZ"; -- High impedance for reading -- Connect outputs from state machine to external signals chipSEL <= '1' when STATE = INIT else '0'; writeEN <= '0' when STATE = WrLEDLo_B else '0' when STATE = WrLEDHi_B else '0' when STATE = WrSsegLo_B else '0' when STATE = WrSsegHi_B else '1'; address <= "000000" when STATE = RdBtnLo_A else "000000" when STATE = RdBtnLo_B else "000000" when STATE = RdBtnLo_C else "000001" when STATE = RdBtnHi_A else "000001" when STATE = RdBtnHi_B else "000001" when STATE = RdBtnHi_C else "000010" when STATE = RdSwt_A else "000010" when STATE = RdSwt_B else "000010" when STATE = RdSwt_C else "000000" when STATE = WrLEDLo_A else "000000" when STATE = WrLEDLo_B else "000000" when STATE = WrLEDLo_C else "000001" when STATE = WrLEDHi_A else "000001" when STATE = WrLEDHi_B else "000001" when STATE = WrLEDHi_C else "000010" when STATE = WrSsegLo_A else "000010" when STATE = WrSsegLo_B else "000010" when STATE = WrSsegLo_C else "000011" when STATE = WrSsegHi_A else "000011" when STATE = WrSsegHi_B else "000011" when STATE = WrSsegHi_C else "000000"; outEN <= '1' when STATE = INIT else '1' when STATE = WrSsegLo_B else '1' when STATE = WrSsegHi_B else '0'; end Behavioral;