Field Programmable Processor Array (FPPA)
Goal: A reconfigurable processor chip to maximize energy efficiency for high-throughput computations on streaming applications for spacecraft.
Sponsor: NASA Goddard Space Flight Center
The FPPA has a reconfigurable data path with 16 processing elements (PEs). Each PE can implement the equivalent of up to seven computer instructions in one clock cycle. It has five 16-bit input ports and one dynamically switchable output port. An internal point-to-point interconnect bus and on-board execution unit set up a synchronous data flow pipeline.
For more detail, check out the 2007 Aerospace Conference paper.
A prototype chip was fabricated on a 0.25µ bulk CMOS process using a radiation-hard-by-design standard cell library. Two challenge problems were programmed and demonstrated on the chip. At an instruction rate of 22.5 million cycles per second, up to 3 Giga-operations/second-watt were observed.
A set of software tools was developed. These include a simulator, a graphical design entry tool, assemblers, a Single-Assignment C compiler, and design optimization tools.
Download the FPPA Programmer’s Guide here.